// SPDX-License-Identifier: GPL-2.0
/*
 * gpadc_ain_csp.c - gpadc csp aux operation
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include "csp_gpadc.h"
#include <mach/debug.h>

/*
 * Get AVCC low voltage detect,
 * return 1 if avcc < 1.5v, return 0 if avcc > 1.5v
 */
u32 csp_ain_low_voltage_det(void *base)
{
	reg_gpadc_ainc_t reg;

	reg.val = READREG32(base + GPADC_AINC_OFF);
	return reg.bits.gpavl_det;
}


/* Set GPADC sample rate */
void csp_ain_set_sample_rate(void *base, AIN_SAMPLE_RATE t)
{
	reg_gpadc_ainc_t reg; /* control register setup */

	reg.val = READREG32(base + GPADC_AINC_OFF);
	reg.bits.src = t;

	WRITEREG32(base + GPADC_AINC_OFF, reg.val);
}


/* Set GPADC sample data average enable */
void csp_ain_set_sda_en(void *base, u32 en)
{
	reg_gpadc_ainc_t reg; /* control register setup */

	reg.val = READREG32(base + GPADC_AINC_OFF);
	reg.bits.sdae = en;

	WRITEREG32(base + GPADC_AINC_OFF, reg.val);
}

/* Set ain channel enable */
void csp_ain_set_en(void *base, u32 source, u32 en)
{
	reg_gpadc_ainc_t reg;

	reg.val = READREG32(base + GPADC_AINC_OFF);
	if (en)
		reg.val |= source;
	else
		reg.val &= ~source;

	WRITEREG32(base + GPADC_AINC_OFF, reg.val);
}

/* Set ain threshold interrupt enable */
void csp_ain_set_int_en(void *base, u32 source, u32 en)
{
	reg_gpadc_ainie_t reg;
	int bit_val = BIT(0) << (source * 4);

	reg.val = READREG32(base + GPADC_AINIE_OFF);
	if (en)
		reg.val |= bit_val;
	else
		reg.val &= ~bit_val;

	WRITEREG32(base + GPADC_AINIE_OFF, reg.val);
}

/* Set ain data interrupt enable */
void csp_ain_set_data_int_en(void *base, u32 source, u32 en)
{
	reg_gpadc_ainie_t reg;
	int bit_val = BIT(1) << (source * 4);

	reg.val = READREG32(base + GPADC_AINIE_OFF);
	if (en)
		reg.val |= bit_val;
	else
		reg.val &= ~bit_val;
	WRITEREG32(base + GPADC_AINIE_OFF, reg.val);
}

/* Get ain interrupt pending */
u32 csp_ain_get_int_pend(void *base)
{
	reg_gpadc_ainis_t reg;

	reg.val = READREG32(base + GPADC_AINIS_OFF);
	return reg.val;
}

/* Clear ain interrupt pending status */
void csp_ain_clr_int_pend(void *base, u32 source)
{
	reg_gpadc_ainic_t reg;

	reg.val = 0;
	reg.val |= source;

	WRITEREG32(base + GPADC_AINIC_OFF, reg.val);
}

/* Get ainx sample data */
u32 csp_ain_get_data(void *base, u32 chan)
{
	u32 val;

	val = READREG32(base + GPADC_AIN_X_DAT(chan));
	return val & 0xFFF;
}

/* Get ainx sample hold data */
u32 csp_ain_get_sh_data(void *base, u32 chan)
{
	u32 val;

	val = READREG32(base + GPADC_AIN_X_HDAT(chan));
	return val;
}

/* Set ainx threashold data */
void csp_ain_set_th_data(void *base, u32 chan, u32 th)
{
	u32 val;

	val = READREG32(base + GPADC_AIN_X_TDAT(chan));
	th = th & 0xFFF;
	val = (val & (~0xFFF)) | th;

	WRITEREG32(base + GPADC_AIN_X_TDAT(chan), val);
}

/* Set ainx I/O output channel */
void csp_ain_init_output(void *base, u32 chan, u32 en)
{
	u32 val = 0;

	val = READREG32(base + GPADC_FIOC_OFF);
	if (en)
		val |= 2 << (4 * chan);
	else
		val &= ~(2 << (4 * chan));

	WRITEREG32(base + GPADC_FIOC_OFF, val);
}

/* Set ainx I/O output polarity */
void csp_ain_set_output(void *base, u32 chan, u32 en)
{
	u32 value = 0;

	value = READREG32(base + GPADC_FDAT_OFF);
	if (en)
		value |= (1 << chan);
	else
		value &= ~(1 << chan);

	WRITEREG32(base + GPADC_FDAT_OFF, value);
}

/* Get ainx I/O output polarity */
int csp_ain_get_output(void *base)
{
	return readl(base + GPADC_FDAT_OFF);
}

